The present invention relates to integrated circuit memory interface circuitry in general, and more particularly to the reordering of requests for efficient access to memories.
Memory devices are fast becoming a bottleneck that is limiting improvements in computer system performance. Part of this is caused by the relative disparity between the increase in processor as compared to memory speed. That is, while processor speed has continued to increase at the well known rate of doubling every 18 to 24 months, memory access times have not kept pace. This gap means that more efficient use of memory bandwidth must be made in order to reduce the effect of this bottleneck and take full advantage of the improved processors.
Data is accessed from a memory by selecting the row and column of one or more memory locations. This is done by asserting specific row and column address signals, referred to as RAS and CAS. The rows in a memory tend to be long traces with many memory cells attached. Accordingly, there is a comparatively long delay when a selected row is changed. Thus, when a row is selected, it is desirable to continue accessing different columns in that row before moving on to another row. This is particularly true if the same bank in the memory is needed.
Memories in computer systems are often made up of multiple dynamic random-access-memory (DRAM) circuits, which may be located in dual-in-line memory modules (DIMMs). These DRAMs are selected using a chip select signal. When changing DRAMs, even if the same row is maintained, there is a delay while a different DRAM is selected.
Accordingly, to increase memory throughput or bandwidth, it is desirable to continue to access a particular row in a bank as many times as possible. If that is not possible, it is desirable to continue to access a particular row in the same DRAM as many times as possible. Failing that, it is desirable to continue accessing the same row. When a new row must be accessed, a page miss has occurred, and the latency of the memory delays the arrival of new data, which possibly disrupts downstream processing.
Thus, what is needed are circuits, methods, and apparatus for reordering access requests to a memory taking these properties of DRAMs into account to increase effective memory bandwidth.